IPC Standarder för kretskort
Alla IPC-dokument kan beställas från Scanditron order@scanditron.se
IPC-A-610E
Acceptability of Electronic Assemblies
IPC-A-610 is the most widely used electronics assembly standard in the world. A must for all quality assurance and assembly departments, IPC-A-610E illustrates industry-accepted workmanship criteria for electronics assemblies through full-color photographs and illustrations. Topics include flex attachment, board in board, part on part, lead free, component orientation and soldering criteria for through-hole, SMT (new termination styles) and discrete wiring assemblies, mechanical assembly, cleaning, marking, coating, and laminate requirements.
IPC-A-610 is invaluable for all inspectors, operators and trainers. Revision E has 809 photos and illustrations of acceptability criteria-165 of them new or updated. This revision has been critically reviewed for clarity and accuracy. The document synchronizes to the requirements expressed in other industry consensus documents and is used with the material and process standard IPC J-STD-001. 400 pages. Released April 2010.
Pris: 880 kr (bok), 920 kr (CD), 1296 kr (Bok + CD).
IPC-A-610D-SW Acceptanskrav för kretskort finns även på svenska!
Pris: 800 kr (bok), 840 kr (CD), 1200 kr (Bok + CD).
Krav för lödda elektroniska kretskort
IPC-J-STD-001E Requirements for Soldered Electrical and Electronic Assemblies
J-STD-001E is recognized worldwide as the sole industry-consensus standard covering soldering materials and processes. This revision includes support for lead free manufacturing, in addition to easier to understand criteria for materials, methods and verification for producing quality soldered interconnections and assemblies. The requirements for all three classes of construction are included. Full color illustrations are provided for clarity. This standard fully complements IPC-A-610E. 54 pages. Released April 2010.
Pris: 720 kr (bok), 760 kr (CD), 1120 kr (Bok + CD)
IPC-J-STD-001D-SW Krav för lödda elektriska och elektroniska kretskort
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inns även på svenska!
Pris: 640 kr (bok), 680 kr (CD), 960 kr (Bok + CD)
Reparation och omarbete av kretskort
IPC-7711/7721B
Rework, Modification and Repair of Electronic Assemblies
IPC-7711/7721B-SW
Omarbetning, modifiering och reparation av kretskort
Major update for lead free support and enhanced inspection guidelines for repairs and modifications! This guide includes everything needed for repair and rework of electronic assemblies and printed circuit boards! IPC-7711B/7721B Rework, Modification and Repair of Electronic Assemblies has received a complete procedure by procedure update to assure applicability to both lead free and traditional SnPb soldered assemblies. Released November 2007.
Även på svenska!
Pris: 1200 kr (bok), 1240 kr (CD), 1760 kr (Bok + CD).
Lödbarhet
J-STD-002C with amendment 1 - NY 2009!
Solderability Tests for Component Leads, Terminations, Lugs, Terminals and Wires
This standard prescribes test methods, defect definitions, acceptance criteria and illustrations for assessing the solderability of electronic component leads, terminations, solid wires, stranded wires, lugs and tabs. This standard addresses both visual acceptance and force measurement solderability criteria for both tin-lead as well as lead-free solder processes. This standard also includes a test method for the Resistance to Dissolution/Dewetting of Metallization to verify that metallized terminations will remain intact throughout the assembly soldering processes. This standard is intended for use by both vendors and users. The Amendment 1 now included in this IPC/ECA J-STD-002C adds an appendix that defines a test protocol for wetting balance testing and also allows the use of production solder pastes of appropriate lead-based and lead free compositions for surface mount simulation testing.
62 pages. Released January 2009.
Pris: 496 kr (bok), 536 kr (CD), 824 kr (BOK + CD).
J-STD-003B
Solderability Tests for Printed Boards
This standard prescribes test methods, defect definitions and illustrations for assessing the solderability of printed board surface conductors, attachment lands, and plated-through holes utilizing either tin/lead or lead-free solders. This standard is intended for use by both vendor and user. The objective of the solderability test methods described in this standard is to determine the ability of printed board surface conductors, attachment lands, and plated-through holes to wet easily with solder and to withstand the rigors of the printed board assembly processes. This standard describes test methods by which both the surface conductors (and attachment lands) and plated-through holes may be evaluated for solderability. Test A, Test B, Test C, Test D and Test E for tin/lead solder processes and Test A1, Test B1, Test C1, Test D1 and Test E1 for lead-free solder processes, unless otherwise agreed upon between vendor and user. Test A and Test C for tin/lead solder processes, Test A1 and Test C1 for lead-free solder processes are to be used as default solderability tests. 36 pages. Released March 2007.
Pris: 416 kr (bok), 456 kr (CD), 640 kr (Bok + CD).
Riktlinjer för implementering av BGA, CSP, HDI, FlipChip
J-STD-012
Implementation of Flip Chip & Chip Scale Technology
This informative document describes the implementation of flip chip and related chip scale semiconductor packaging technologies. The areas discussed include design considerations, assembly processes, technology choices, application and reliability data. Chip packaging variations include flip chip, HDI, micro BGA, micro SMT and SLICC. Also provides general information on implementing flip chip and chip scale technologies for creating multichip modules, I/C cards, memory cards and very dense surface mount assemblies. Developed by IPC, EIA, MCNC and Sematech. 113 Pages. Released January 1996.
Pris: 656 kr (bok), 736 kr (CD), 992 kr (Bok + CD).
J-STD-013
Implementation of Ball Grid Array & Other High Density Technology
This document establishes the requirements and interactions necessary for printed board assembly processes for interconnecting high performance/high pin count IC packages. Includes information on design principles, material selection, board fabrication, assembly technology, testing strategy and reliability expectations based on end-use environments. Developed by IPC, EIA, MCNC and Sematech. 96 Pages. Released July 1996.
Pris: 656 kr (bok), 736 kr (CD), 992 kr (Bok + CD).
J-STD-030
Guideline for Selection and Application of Underfill Material for Flip Chip and Other Micropackages
This document provides users of underfill material with guidance in selecting and evaluating underfill material. Underfill material is used to increase reliability of electronic devices by two methods: alleviate CTE mismatch (between the electronic package and the assembly substrate) and/or increase mechanical strength. Materials used in underfill applications should not adversely affect device reliability (e.g. ionic impurities, alpha emitters) nor degrade electrical performance. When correctly selected and applied, underfill material should increase the life of the assembled solder joints. The following three types of currently available, underfill materials addressed in this document are: Capillary Flow Underfill, No-Flow/fluxing Underfill and Removable/Reworkable Underfill. 33 pages. Released September 2005.
Pris: 656 kr (bok), 736 kr (CD), 992 kr (Bok + CD).
IPC-7094
Design and Assembly Process Implementation for Flip chip and Die Size components
Implementing flip chip technology in a direct chip attach (DCA) assembly presents some unique challenges for design, assembly, inspection and repair personnel. IPC-7094 delivers useful and practical information to anyone who is currently using or contemplating developing products that employ the very complex and high density methods needed for the flip chip technology. The concepts have become especially important due to the pressures to manufacture products that have components very closely integrated or are intended for portable and hand held applications. The major emphasis of the new standard is to provide information to those companies transitioning to this miniaturization technology with emphasis on system level issues, flip chip and die size assembly, and the requirements for board and module level reliability.
In addition to providing guidelines for flip chip inspection, IPC-7094 also addresses the design of the initial element and how the die can be evaluated during its development process with a goal toward simplification of the final assembly. Items that are discussed include outsourcing manufacturing and the procurement of known good die in order to optimize the return on investment when developing products that use flip chip technology. 75 pages. Released February 2009.
Pris: 824 kr (bok), 864 kr (CD), 1152 kr (Bok + CD).
IPC-7095B
Design and Assembly Process Implementation for BGAs
Implementing Ball Grid Array (BGA) and Fine-Pitch Ball Grid Array (FBGA) technology presents some unique challenges for design, assembly, inspection and repair personnel. IPC-7095B delivers useful and practical information to anyone currently using BGAs or considering a conversion to area array packaging formats, This has become especially important due to the change in the alloys being used, both on the BGA packages and the solder alloy used to attach it to the printed board land pattern. The major emphasis of Revision B is to provide information to those companies transitioning from the standard tin/lead reflow processes to those that use lead-free materials in the assembly of BGA type components.
In addition to providing guidelines for BGA inspection and repair, IPC-7095B also addresses reliability issues and the use of lead-free joint criteria associated with BGAs. There are many new photographs of X-ray or endoscope illustrations to identify some of the characteristics that the industry is experiencing in the implementation of BGA assembly processes as well as void process indicators.
152 pages. Released March 2008.
Pris: 824 kr (bok), 864 kr (CD), 1152 kr (Bok + CD).